Wait until PC = X"0008" - we only have 8 instructions Reset<= '1' - reset control unit wait for I_clk_period - wait a cycles We can then initialize the unit in our main test bench body. O_data <= ram(to_integer( unsigned(I_addr(2 downto 0)))) Ram(to_integer( unsigned(I_addr(2 downto 0)))) <= I_data O_data : out STD_LOGIC_VECTOR (15 downto 0)) Īrchitecture Behavioral of ram_tb is type store_t is array (0 to 7) of std_logic_vector(15 downto 0) I_data : in STD_LOGIC_VECTOR (15 downto 0) I_addr : in STD_LOGIC_VECTOR (15 downto 0) We get back into the Xilinx ISE project, adding out new pc_unit.vhd with the various input and output ports we need.Įntity ram_tb is Port ( I_clk : in STD_LOGIC Our PC unit then looks like this functional unit. We can use a 2-bit opcode input to select one of these operations.
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